The present invention relates to a method of driving an image sensor (for example, a linear contact image sensor) for reading images in a facsimile, image scanner, digital copying machine, X-ray imaging apparatus, or the like and, more particularly, to removal of fixed pattern noise (FPN) arising from inter-chip differences or deviations in a contact image sensor in which a plurality of semiconductor photosensor chips are mounted on a mounting substrate.
In recent years, in the field of linear photo-electric conversion devices, an equal-magnification (magnification=1) contact image sensor in which a plurality of semiconductor photosensors are mounted has been extensively developed in addition to CCDs using reducing optics.
FIG. 1A is a partial block diagram showing the arrangement of a conventional contact image sensor having an amplifier element, which is disclosed in Journal of Television Society Vol. 47, No. 9 (1993), pp. 1180. In this contact image sensor, a plurality of amplifier type semiconductor photosensor chips having amplifier elements in units of pixels are mounted. Especially, FIG. 1A shows the arrangement of a single sensor chip.
The output from one sensor module is externally output via an analog switch 37. FIG. 1B shows a state wherein a plurality of sensor chips are connected. In order to enable the output of a specific chip, the analog switch 37 of that chip is energized.
As shown in FIG. 1A, one sensor chip comprises a plurality of sensor elements (phototransistors 9), an output line 3 (4) which commonly receive the outputs from these transistors 9, differential amplifier 33, clamping circuit 204, and buffer amplifier 36, the above-mentioned analog switch 37, and the like.
In the image sensor, since fixed pattern noise (FPN) resulting from variations of the amplifier elements used for a plurality of pixels is produced, FPN produced in the chip is removed by calculating the difference between a light signal (S signal) and noise signal (N signal) in a dark state (to be referred to as an “S-N method” hereinafter for the sake of simplicity) in the prior art shown in FIG. 1A.
FPN removal using the S-N method in the image sensor shown in FIG. 1A will be described below with reference to FIGS. 1A and 2 (timing chart).
In FIG. 1A, the bipolar transistor 9 constructs a sensor portion of a photo-electric conversion element. Each transistor 9 is connected to a MOS transistor 27 (28), MOS transistor 31 (32), capacitances CTS1 and CTN 2 which are reset by the reset signal φCR, and MOS transistor 25 (26), and the MOS transistors 25 and 26 of the respective bits are connected to the common output lines 3 and 4. Reference symbols CHS and CHN denote capacitances for the output lines 3 and 4. The output lines 3 and 4 are connected to the differential amplifier 33 via voltage-follower amplifiers 13a and 13b. 
Upon irradiation of light onto the sensor 9 of the photo-electric conversion element, a light signal (i.e., a charge) corresponding to its light amount hν (h is a Planck constant, and ν is the frequency of the light) is accumulated on the PN junction of the emitter-follower transistor 9. Upon completion of accumulation, the transistor 9 is set in a floating state (by turning off φERS), and φTS is turned on to transfer the charge accumulated on the PN junction to the light signal holding capacitance CTS1. Subsequently, a reset pulse φERS is turned on to reset the sensor (transistor 9). At this time, the charge transferred to the capacitance CTS1 contains noise components. After that, φTN is turned on to transfer a noise (N) signal of the sensor to the noise signal holding capacitance CTN2. Again, a reset pulse φBRS is turned on to enable a MOS transistor 29, and the reset pulse φERS is turned on to enable a MOS transistor 30. Since the MOS transistors 29 and 30 are ON, the sensor transistor 9 is reset and then starts the next accumulation.
Some components of the charges accumulated on the CTS1 and CTN2 are respectively shifted to the output line capacitances CHS and CHN during the next accumulation. This operation is called “capacitive division” for the sake of simplicity since the original charges accumulated on CTS1 and CTN2 are divided as a result of movement of the charges between the two capacitances. The “capacitive division” is activated by the MOS transistors 25 and 26 when a control timing signal φN is ON. The “capacitive division” will be explained below.
In order to reset holding capacitances CHS 7 and CHN 8, MOS transistors 5 and 6 are turned on by a signal φHC. After these capacitances are reset, the MOS transistors 25 and 26 are turned on by the timing signal φN output from a shift register (not shown). When the MOS transistors 25 and 26 are ON, data in the light signal holding capacitance CTS1 and noise signal holding capacitance CTN2 (some components of charges) are respectively transferred to the capacitances CHS7 and CHN 8, connected to the common output lines 3 and 4. Consequently, the potential that appears on the output line 3 (4) is determined by the ratio between the capacitances CHS 7 and CTS 1 (the ratio between CHN 8 and CTN 2). The potential on the output line 3 (4) is amplified by the differential amplifier 33 via an amplifier 13a (13b).
Although not shown in FIG. 1A, as described above, one sensor chip has sensor elements 9 for a plurality of bits. In order to read out the sensor output of the next bit, the capacitances CHS 7 and CHN 8 are reset by turning on the MOS transistors 5 and 6, and a drive signal φN for that bit is then supplied to read out data accumulated on the capacitances CTS and CTN to the common capacitances CHS 7 and CHN 8.
By repeating such shift operation, the charges accumulated on the sensors (transistors 9) of the respective bits are read out to the capacitances CHS 7 and CHN 8. Voltages induced on the capacitances CHS 7 and CHN 8 are input to the differential amplifier 33 via the voltage-follower amplifiers 13a and 13b. 
Fixed pattern noise FPN in the sensor IC mainly arises from variations of hFE or the like of the bipolar transistors 9 of the respective pixels (bits). Such variations are reflected in the charges accumulated on the holding capacitances CTS and CTN. FPN removal using the S-N method removes noise resulting from hFE variations of the bipolar transistors 9 in units of pixels by detecting any level differences between the signal lines by the differential amplifier 33 upon reading out the charges accumulated on the holding capacitances CTS and CTN onto the common signal lines 3 and 4.
The S-N method using the differential amplifier 33 is effective for removing FPN produced in the sensor chip.
However, in case of the equal-magnification contact image sensor in which a plurality of photosensors are mounted, since a plurality of linear line sensor chips are cascade-connected, as shown in FIG. 1B, as it is of contact type, the differential amplifiers 33 and buffer amplifiers 36 are arranged in units of chips. Among the differential amplifiers 33 (or buffer amplifiers 36) of the different chips, the DC components of the output voltages vary due to variations of offset potentials. Such variations of the DC offset voltages among chips will be referred to as “FPN resulting from inter-chip differences (inter-chip FPN)” in contrast to “FPN produced in the chip (intra-chip FPN)” in this specification.
The above-mentioned S-N method is not effective for inter-chip FPN.
In the image sensor shown in FIG. 1A, the clamping circuit 204 copes with inter-chip FPN resulting from the differential amplifier 33. That is, the clamping circuit 204 is constructed by a capacitance 34 for cutting DC components from the output from the amplifier 33, and a MOS transistor 35 for fixing to earth level the potential between this capacitance 34 and the input portion of the amplifier 36, that shifts to the minus side. With this arrangement, the clamping circuit 204 can prevent inter-chip FPN attributed to the differential amplifier 33.
However, the present inventors found that it is difficult to remove inter-chip FPN arising from the offsets of the output buffer amplifier 36 even by the prior art technique shown in FIG. 1A.
Especially, when the initial stage of the output buffer amplifier 36 adopts a MOS top arrangement (in which the MOS transistor is located on the input side), since threshold value unbalance of that MOS influences the offsets, offset variations of, e.g., around 10 mV are produced among the output buffer amplifiers 36 of different chips. Even after a plurality of sensor chips are mounted, as shown in FIG. 1B, FPN of around 10 mV is produced.
Hence, when a high-gradation image is to be obtained using the conventional image sensor, dark correction is required in units of chips to assure its dynamic range, and the cost required for system design and manufacture increases.
In the prior art, each sensor chip includes a large-scale analog circuit such as a sensor, holding capacitances, and the like, and 10 to 20 chips are mounted. For this reason, the chip area for the analog circuit portion increases, and it is hard to reduce cost.
Furthermore, each sensor chip includes both a digital circuit such as MOS transistors for light signal read and reset, and the aforementioned analog circuit, and the sensor output is readily influenced by noise produced by the digital circuit.